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    4,547 verilog vhdl робіт знайдено, ціни вказані в USD

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    $460 (Avg Bid)
    $460 Сер. заявка
    2 заявки
    Implementation of Cryptographic Algorithm for an IoT application 1 година left
    ПІДТВЕРДЖЕНО

    I need to implement an FPGA-based cryptographic algorithm for a decentralized IoT application in Vivado Design Suite. Anyone who has a good command of Verilog implementation for FPGA in Vivado can discuss with me for further details.

    $229 (Avg Bid)
    $229 Сер. заявка
    6 заявки

    We need a project done in Morse code encoder and decoder in VHDL. Our project contains 2 parts a transmitter and receiver. The transmitter part receives the text(ASCII) from the PC(user) via UART receiver and transmits the text to morse code encoder(converts text to morse code). The morse code pattern then is sent to an led. Dot(.) corresponds to LED on and dash(-) LED off. The receiver part has a photo diode which reads the blinking of the led(morse code) and data is transmits to Morse decoder where it is converted back to ASCII. The converted ASCII is then transmitted to end user PC for display. We have already designed the top level top level block diagram. we now need the source codes(entity and architecture) for the blocks and test benches for all blocks for simulation...

    $27 (Avg Bid)
    $27 Сер. заявка
    7 заявки
    STM32CubeIDE and VHDL quartus Закінчився left

    STM32 toolchain and also vhdl design with report describing the procedures

    $38 (Avg Bid)
    $38 Сер. заявка
    4 заявки
    quartus and modulsim Закінчився left

    i want some vhdl coding simulating with test bench on modulsim and a report

    $57 (Avg Bid)
    $57 Сер. заявка
    7 заявки
    FPGA Project Закінчився left

    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

    $21 / hr (Avg Bid)
    $21 / hr Сер. заявка
    18 заявки

    This project requires basic knowledge of digital electronics and VHDL coding.

    $14 / hr (Avg Bid)
    $14 / hr Сер. заявка
    12 заявки
    Digital Electronics and VHDL Project Закінчився left

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $21 - $69
    Прихований
    $21 - $69
    5 заявки
    Digital Electronics and VHDL -- 3 Закінчився left

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $42
    Прихований
    $7 - $42
    6 заявки
    Digital Electronics and VHDL -- 2 Закінчився left

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $42
    Прихований
    $7 - $42
    7 заявки
    Digital Electronics and VHDL Закінчився left

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $35
    Прихований
    $7 - $35
    5 заявки

    Professional and proficient in the following areas Boolean Algebra and Logic Design  Number systems  Basic Theorems of Boolean Algebra  Canonical and Standard Forms  Logic Gate Implementations and Characteristics: ...Logic  Latches  Flip Flops  Finite-State Machine (FSM) Model  Synthesis and Analysis  Designing State Machines using State Diagrams  Designing State Machines using ASM (Algorithmic State Machine) Charts  State Minimisation, Optimisation and Timing. Hardware Description Languages (VHDL)  Combinatorial descriptions  Delta Delays  VHDL hierarchy (Entities, modules, instantiation)  Language constructs (conditional assignment, selected assignment)  Synchronous descriptions (processes, if, case)  VHDL test benches  Synthesis considerations

    $15 (Avg Bid)
    $15 Сер. заявка
    10 заявки
    Ethernet RTL(Verilog) Tutor Закінчився left

    Explain and help understand Ethernet MAC/PHY RTL from github. Required: - Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP. Meetings will be conducted via zoom/meets. Thank you!

    $568 (Avg Bid)
    $568 Сер. заявка
    8 заявки
    Verilog program to fpga Закінчився left

    Program on vivado (verilog), morse code. Binary for "BASYS 3" fpga, simulation, files...etc More details via chat

    $43 (Avg Bid)
    $43 Сер. заявка
    8 заявки

    I need to implement an Ed25519 Algorithm in Verilog for FPGA implementation that can properly simulate on Xilinx Vivado Design Suite. The complete algorithm code is already available in C language and I want to convert it into Verilog. Link:

    $231 (Avg Bid)
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    8 заявки

    Given any Verilog netlist of a digital circuit in gate-level format, the code should extract critical path. Critical path is the longest path from input to output port. There could be multiple inputs/outputs in a given circuits. Critical path can be the longest path from any input to any output based on the connections in the circuit.

    $13 (Avg Bid)
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    5 заявки
    vhdl RISC processor coding Закінчився left

    I need a vhdl master to code a RISC processor with multiple components. I will give the detailed information.

    $61 (Avg Bid)
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    5 заявки
    fibonacci series generator Закінчився left

    need to make truth table and Circuitry Design and verilog code and testbench for fibonacci series generator

    $35 (Avg Bid)
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    16 заявки
    FPGA Developer Закінчився left

    I have rich experience with FPGA I developed FPGA based IDS(Intrusion Detection System) I am strong at C, C++, Verilog and son on

    $550 (Avg Bid)
    $550 Сер. заявка
    5 заявки

    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

    $17025 (Avg Bid)
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    12 заявки
    Help with VHDL Закінчився left

    I have to implement a pipelined DLX processor. I have already constructed the single staged processor. However, I will need you to do the pipelining part which would include the pipelined control, and relevant harard detectors, forwarding unit, and bypassing mechanisms. The project now has been implemented using a supermodular approach where I have tried to make the VHDL codes for the smallest units and then built them upwards in the schematic. I will need the schematic of the pipelined dlx too. here is the drive link with all the files for your reference I have a certain benchmark to run which i will share once i get to design it but the i will need the isim simulations of the entire processor as a proof that

    $130 (Avg Bid)
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    4 заявки
    VHDL and risc-v LAB work . Закінчився left

    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

    $30 - $250
    Прихований
    $30 - $250
    9 заявки
    VHDL and risc-v LAB work Закінчився left

    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

    $30 - $250
    Прихований
    $30 - $250
    5 заявки
    assistance with ripes vhdl and risc-v Закінчився left

    hello, please contact me if you are proficient in the fields above

    $200 (Avg Bid)
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    3 заявки

    Assalam o alaikum !!! We are looking for electrical engineers to join our team and work on different projects related to following domains of electrical engineering: 1) Control System 2) Satellite communicati...related to following domains of electrical engineering: 1) Control System 2) Satellite communication 3) Radio frequency and microwave circuit design 4) VLSI techniques 5) Radar theory and satellite communication 6) Intelligent and adaptive systems 7) Digital design 8) Asic design Freelancers must be proficient in following: 1) Matlab / Simulink 2) Proteus 3) Multisim 4) pspice 5) LTspice 6) VHDL/Verilog coding What I am expecting: 1. Dedication to the work 2. On time delivery of work without any delay 3. Well arranged and properly formatted reports with plagiaris...

    $154 (Avg Bid)
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    11 заявки

    We are looking for electrical and electronics engineers with good experience in following areas: • Embedded C Programming. • VHDL/Verilog, LabVIEW/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. Feel free to place your bid and mention your areas of expertise in your proposal. we highly encourage new freelancers to apply for this post.

    $161 (Avg Bid)
    $161 Сер. заявка
    23 заявки

    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

    $4634 (Avg Bid)
    $4634 Сер. заявка
    7 заявки
    Labwork assistance Закінчився left

    I have a few labs im struggling with and they all follow one another. It requires VHDL, RARS and Ripes. Please contact me so I can show you the details and so we can get started on this. Thanks!

    $158 (Avg Bid)
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    Fpga project Закінчився left

    1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle". 2. "a" state: In state "a", if fill_water is 1(tha...state of the machine. In "c" state, if the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c". and in state a it depends on weight for example : 0-2 kilo 3 seconds to fill water 3-5 kilos 5 seconds 6-7 kilos 8 seconds for the weight 3bit...

    $53 (Avg Bid)
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    11 заявки
    Integrated circuit design Закінчився left

    Verilog/VhDL FPGA Asic Electronics Microcontroller

    $91 (Avg Bid)
    $91 Сер. заявка
    15 заявки
    Integrated circuit design -- 2 Закінчився left

    Hey I need someone who knows how to deal with integrated circuit design and vhdl

    $18 / hr (Avg Bid)
    $18 / hr Сер. заявка
    12 заявки

    Hi, just to make sure. Do you have the Nexys 4 DDR board and vivado 2020.1 installed? Also, Do you have knowledge of multithreaded OS, in particular FreeRTOS? detail will be share in chat box

    $272 (Avg Bid)
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    4 заявки

    The instruction set for the processor RISC-V should be expanded. Hardware implementation of RISC-V processor with pipeline is already done (There is 5 stages of pipeline: Fetch, Decode, Execute, Memory and WriteBack). VHDL files are in attachment. The task is to upgrade this processor with 20 new instructions. For each instructions there is possibility of appearance of the hazard. Every hazard must be resolved. In the documentation there is explanation for the hazards as well as their elimination. Also, in VHDL files, there is implementation of blocks which remove hazards. Just ADD, AND, SUB and OR instructions are implemented in RISC-V. Current implementation of RISC-V support just this 5 instructions, so update of RISC-V is need it for 20+ new instructions For interactive ...

    $115 (Avg Bid)
    $115 Сер. заявка
    3 заявки

    Hi, just to make sure. Do you have the Nexys 4 DDR board and vivado 2020.1 installed? Also, Do you have knowledge of multithreaded OS, in particular FreeRTOS?

    $111 (Avg Bid)
    $111 Сер. заявка
    4 заявки
    Single cycle mips proccessor Закінчився left

    design a single cycle mips proccessor computer Architecture vhdl

    $150 (Avg Bid)
    $150 Сер. заявка
    10 заявки
    Integrated circuit design Закінчився left

    Knowledge in integrated circuit design and vhdl

    $16 / hr (Avg Bid)
    $16 / hr Сер. заявка
    9 заявки
    FPGA DESIGN - Verilog and Testbench Закінчився left

    There are about 10 prompts (design + testbench) that need to be written in Verilog. Message me personally for the prompts. I need it done as soon as possible.

    $26 (Avg Bid)
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    9 заявки
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    1 заявки
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    Project for Waleed A. Закінчився left

    Hi Waleed A., are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    Project for Chhanda H. -- 2 Закінчився left

    Hi Chhanda H., are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    Project for Quan D. -- 2 Закінчився left

    Hi Quan D., are you familiar with verilog vivado?

    $25 (Avg Bid)
    $25 Сер. заявка
    1 заявки
    Project for Krishna G. Закінчився left

    Hi Krishna G., are you familiar with verilog vivado?

    $25 (Avg Bid)
    $25 Сер. заявка
    1 заявки
    Project for Iqra J. Закінчився left

    Hi Iqra J., are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    $25 Сер. заявка
    1 заявки
    Project for Abdullah E. Закінчився left

    Hi Abdullah E.,are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    Project for Chhanda H. Закінчився left

    Hi Chhanda H., are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    Project for Quan D. Закінчився left

    Hi Quan D.,are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки
    Project for Minu G. Закінчився left

    Hi Minu G., are you familiar with verilog vivado?

    $20 (Avg Bid)
    $20 Сер. заявка
    1 заявки