Verilog vhdlроботи

Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

I am seeking a highly skilled hardware design engineer for a fixed-term academic project. The objective is to design, implement, and verify a complex 32-bit MIPS general-purpose CPU. The project will be developed using VHDL or Verilog on the EDA Playground online simulation environment. This project is divided into two main phases with two distinct deadlines. The freelancer must be capable of handling complex processor architecture, including floating-point unit integration, pipelining, and cache memory design. Phase 1: 32-bit MIPS Processor with Custom FPU (Deadline: 17/11) This phase involves building the core single-cycle processor and integrating a custom floating-point unit (FPU). Step 1.1: Base 32-bit MIPS Design Design and implement the datapath for a 32-bit MIPS ...

I need a VHDL IP core that sits between two AXI4-Stream FIFOs, ingests a packet of N values, performs a simple arithmetic tweak, and pushes the result back out. Here is the exact scope: • Interface: one AXI4-Stream slave for input, one AXI4-Stream master for output. • Packet size: parameterised (e.g. default 8 words, 32-bit each). • Operation: addition with a constant, hard-coded inside the source (no run-time configuration needed). • Overflow handling: if more than N words arrive before TLAST, raise a dedicated error line and discard the surplus. • Deliverables: – Readable, synthesizable VHDL source for the core. – A self-checking test-bench (ModelSim/Questa or similar) that drives typical and corner-case traffic, shows t...

...constraints file (SDC) handling clock, IO delays, and false/multicycle pathsPower planning and optimization for low power operation (optional if applicable)Final GDSII or layout database for tapeout or further place-and-route stepsTiming reports demonstrating timing closure with specified constraintsVerification of design correctness via post-layout simulation support files (optional)Provided Files:RTL Verilog sources for SPI, I2C, UART modules, and the top-level Multi-Protocol Conversion Unit (mpcu_all.v and associated testbenches)Protocol conversion logic (conv_protocl.v)Research and design analysis paper ("")Sample SDC constraints file (can be enhanced/modified as per target technology)Constraints and Environment:Clock frequency:

I’m planning an automotive-grade ASIC focused on reliable sensor interfacing and need a seasoned embedded engineer to shape the initial blueprint. Here’s what I’m looking for: • A high-level architecture that defines power domains, I/O pinout, and core logic blocks dedicated to sensor data acquisition. • Block-level Verilog or VHDL stubs for the key sensor interface modules so I can validate feasibility on my end. • Basic timing, power, and temperature estimates suitable for an automotive environment (-40 °C to 125 °C). • A short BOM or technology recommendation—foundry node, package type, and any external components essential for stable operation. Keep the scope to this early concept stage; I’m not seeki...

...you already have production experience inside a finance-sector environment and can demonstrate battle-tested results. Code quality, reproducibility and operational safety are non-negotiable, so I’ll look for evidence of rigorous version control, unit testing and live-to-backtest parity. Typical deliverables we’ll scope together include: • A clean, well-documented module (Python, C++, or Verilog/VHDL where relevant) that slots into the existing code base. • A back-test that matches live fills within agreed slippage bands. • Automated CI/CD or MLOps workflow that promotes research models to production with roll-back capability. If you’ve shipped latency-sensitive code, built risk engines, streamed tick data at scale or deploy...

I need a Verilog implementation of a CNN accelerator with a DRAM interface. The accelerator should perform matrix multiplication on fixed-size matrices. The DRAM interface should be DDR3. Key requirements: - Functionality: Matrix multiplication only - Matrix type: Fixed-size matrices - DRAM interface: DDR3 Ideal skills and experience: - Proficiency in Verilog - Experience designing CNN accelerators - Knowledge of DRAM interfaces, specifically DDR3 - Strong background in digital design and hardware description languages Please provide relevant experience in your bids.

I’m looking for a clean Verilog design that realises a 3-bit synchronous counter, counts in ordinary binary from 0 through 7, and drives a single seven-segment display mounted on a Zynq MP FPGA board. Everything will be built and programmed inside Xilinx Vivado, so please target the standard Zynq MPSoC constraints and make sure your files open and synthesise without warnings there. What I need from you is the complete module for the counter itself, the segment-decoder logic, a concise test-bench that proves the 0-to-7 sequence, and a Vivado project or clear instructions that allow me to generate the bitstream and dump it straight to the board. Timing must be synchronous to the on-board clock, and resets should be active-low so I can link them to a push-button. Acceptance cri...

I need a concise, synthesizable Verilog finite-state machine that detects the bit sequence 1011 (with overlap) and drives a single-cycle “found” pulse when the pattern appears. The design must target a Xilinx Zynq board and be built in Vivado 2022.1. Please use binary state encoding; that choice is fixed for this job. Here’s how I’d like the work delivered: • Source files: top-level Verilog module, separate testbench, and any support files. • Constraints: an XDC pinout I can adapt to my board. • Vivado 2022.1 project archive, including synthesis and implementation reports. • Generated .bit file so I can program the FPGA immediately. • Short read-me explaining the state-transition diagram, how overlap is handled, and h...

I have to count very fast digital pulses—up to 200 MHz—using a Xilinx XC7S50 (Spartan-7, BGA package). The design must implement four independent 64-bit counters that share a common asynchronous reset line brought out to a single input pin. Read-back of the counts will happen over an SPI link, so the HDL should expose a simple, register-mapped SPI slave. Alongside the synthesizable VHDL or Verilog, I also need practical guidance on the hardware: how to lay out or select a compact development board that suits the XC7S50, ensures the 200 MHz signal integrity, and brings out the reset and SPI pins cleanly. If an off-the-shelf board will work, point me to it; if a custom carrier is wiser, outline the critical constraints (clocking, decoupling, pin assignments, oscill...

...from the following building blocks: • Operational Amplifiers (Op-Amps) • Digital-to-Analog Converters (DACs) • A Howland Current Pump topology If you have a more elegant approach that still meets the accuracy requirement I’m open to hearing it, but the solution must remain feasible for small-batch assembly. Deliverables • Complete walkthrough of how to connect components to FPGA • Verilog/VHDL code for the FPGA, including a simple register map that lets a microcontroller or PC set each channel’s current (positive or negative) and trigger synchronous updates. • Well-commented simulation files showing stability of the analog loop and timing closure in the FPGA. I will provide the desired mechanical outline for the...

... Deliver source code, firmware binaries, and short documentation. Ensure the firmware enumerates correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-chea...

...the traces and a thorough Differential Side-channel Analysis around the cryptographic routines. For the protocol work you will decode every APDU, verify the cryptograms and give me a clear view of transaction validity. On the DSA side I expect you to pinpoint any leakage observable in the power or timing data and explain how it might be exploited. Deliverables 1. Commented HDL (VHDL/Verilog/SystemVerilog) or equivalent scripts that ingest the captured signals and output human-readable traces for both card types. 2. Clear test results showing data being captured 3. A concise report detailing transaction validation results plus your DSA findings, complete with annotated graphs and evidence. 4. Practical recommendations for mitigation or deeper follow-up t...

I’m building a motion-control stage that relies on a quadrature rotary encoder operating behind a 100 MHz system clock. I need a compact FPGA module—Verilog or VHDL is fine—that reliably handles three tasks in real time: position tracking, speed calculation and direction detection. Your logic should sample the A/B channels cleanly at the full clock rate, debounce or filter any chatter, and maintain a signed position counter that never rolls over within a 32-bit range. From that same data stream I want a direction flag plus a speed value updated once per programmable interval (ideally every millisecond). All three results must be exposed as clean digital outputs that the rest of my design can pick up on the same clock edge. Please include a short testbench ...

I need a compact DVB packet processor written in Verilog that runs on a Lattice iCE40 FPGA. The sole task is packet filtering—specifically PID filtering—restricted to one selected PID at a time. Scope • RTL design in clean, synth-ready Verilog targeting the iCE40 HX or UP family • Functional testbench that feeds 188-byte TS packets, demonstrates correct acceptance of the chosen PID, and drops everything else. • Synthesis script (nextpnr + IceStorm or Lattice Radiant) showing timing closure at 27 MHz TS clock or better. • Resource-usage report so I can judge fit against the device’s limited LUT/BRAM budget. • Simple register or constant that lets me change the target PID before build time; run-time reconfiguration via a sm...

... Deliver source code, firmware binaries, and short documentation. Ensure the firmware enumerates correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-chea...

...in FOGA or FPGA programming (Verilog, VHDL, or equivalent) Proven experience with high-frequency signal acquisition and processing Strong understanding of rotary encoder interfaces (quadrature, absolute, etc.) Ability to design and implement real-time systems Experience with timing constraints, debouncing, and signal filtering Integration with microcontrollers or external systems (if needed) Efficient use of memory and resources on the chip Technical Specs: Encoder Frequency: Up to 100MHz Signal Type: Please specify if you need quadrature, SSI, BiSS-C, or other formats Platform: You can specify FPGA family (e.g., Xilinx, Altera) or leave open for bidder suggestions Optional: Provide info on existing hardware (if available) Deliverables: Source code (Verilog/VHDL...

I’m building a simple digital-lock proof-of-concept on a Nexys Artix-7 board using Vivado. At this stage the only feature I need is a basic lock-out mechanism—no fingerprint, keypad, or card reader yet. I already have a rough plan and can handle the introductory VHDL/Verilog myself, but I want an FPGA expert to: • Review and refine my high-level design so the lock-out logic is clean and synthesizable. • Supply or polish compact, well-commented code blocks where my initial draft falls short. • Walk me through synthesis, implementation, and on-board testing in Vivado, stepping in to debug timing or constraint issues that pop up. I’ll run the hardware on my end; you’ll provide guidance via chat or quick screenshares and, when necessar...

We are looking for a skilled FPGA Design Engineer with solid experience in VHDL development and FPGA toolchains (Vivado, Quartus). You will collaborate remotely using our servers and follow a structured workflow that includes version control, automated analysis, and verification. The ideal candidate is proactive, detail-oriented, and comfortable working on real FPGA design tasks, from module development to system-level integration. Responsibilities Design, implement, and verify VHDL modules for FPGA-based systems. Work with Xilinx (Zynq) and Intel (Altera) FPGA platforms. Integrate and debug high-speed serial protocols such as Aurora, SDI, HDMI, 10 GbE, and other Gbps transceiver-based links. Support signal processing and video processing implementations on FPGA. Contribute...

...existing RISC-V core and dramatically speeds up convolutional layers in a CNN inference pipeline. The sole metric I care about is throughput: higher frames-per-second at the same clock. Power savings or memory tweaks are nice side effects, but raw speed is what will decide success. Target platform is an FPGA prototype, so the RTL should be synthesis-ready and resource-aware. I am comfortable with Verilog, VHDL, SystemVerilog, as long as the code is clean and well-documented. AXI4 or an equally common on-chip bus is expected for host interaction, but I’m open to your suggestion if it fits the RISC-V ecosystem better. Key points you should hit • A custom instruction or tightly-coupled accelerator port on the RISC-V CPU for launching 2-D convolutions. • ...

...digital circuit design and we’re looking for an ECE-trained partner who can jump in quickly. The work ranges from drawing clean schematics and selecting ICs to running simulations and walking us through timing or power considerations before we commit to the board. Typical tasks you might handle include: • Translating our functional block diagrams into gate-level or HDL implementations (Verilog/VHDL welcome). • Producing simulation files and screenshots that prove the logic works (Multisim, Proteus, Quartus, ModelSim—whatever you are comfortable with). • Supplying concise notes so the rest of the team can reproduce or extend the design. If you have breadboard or FPGA experience and can show a quick demo video, that’s a bonus but ...

...Once the high-level structure is solid I will extend the effort into detailed logic-gate diagrams and the encoding of every operation, so choices made now must scale. Here is what the finished package should cover: • Block-level architecture diagram that shows ALU, registers, control unit, I/O and clock domains. • Signal-flow description (timing, control, data) clear enough to drop into VHDL / Verilog or a schematic capture tool. • Instruction or operation encoding table that unambiguously links op-codes to control word bits. • Written rationale for design decisions and resource estimates (gate count, memory, timing margins). • Any simulation or verification artefacts that prove the arithmetic units behave correctly. Submit a detailed pro...

I need an experienced FPGA developer to design, program, and test an SDI fiber converter. The converter should support video signal conversion for HD-SDI and 3G-SDI formats. It must have SFP and SDI input & output i...conversion for HD-SDI and 3G-SDI formats. It must have SFP and SDI input & output interfaces. Key Requirements: - Design and implement video signal processing algorithms - Program FPGA to handle HD-SDI and 3G-SDI formats - Integrate fiber optic and SDI output interfaces - Thorough testing to ensure reliability and performance Ideal Skills and Experience: - Proficiency in FPGA programming (Verilog/VHDL) - Experience with video signal processing - Knowledge of SDI and fiber optic interfaces - Strong troubleshooting and testing skills Looking for high-qu...

I need a clean, Segmened Analysis and Necessity first search algorithm implementation using python then reduced coefficients constants will be given as input to rmcm block as hardcoded values in Verilog well-structured Verilog implementation of an FIR filter that follows the RMCM (Reconfigurable Multiple Constant Multiplication)architecture. The goal is strictly functional verification, so everything happens inside ModelSim; no FPGA bitstream or ASIC sign-off is required. The code must be synthesizable, but the only deliverables I need at this stage are: • Verilog source files that realise the RMCM-based FIR • A self-checking ModelSim test-bench with a small set of example input vectors and expected outputs • Simulation snapshots or log files that ...

...variety of ongoing and upcoming projects. If you're passionate about solving real-world engineering problems and want to work with a dynamic, growing team, this is your opportunity! Areas of Expertise We’re Looking For: We welcome experts in any (or multiple) of the following domains: * ✅ Digital Electronics * ✅ Power System Analysis * ✅ MATLAB / Simulink * ✅ ETAP * ✅ PowerWorld Simulator * ✅ Verilog HDL * ✅ FPGA Design & Simulation What You’ll Do: * * Collaborate with our in-house engineers on project-based tasks * Deliver simulation, analysis, and modeling results * Optimize systems for real-world application * Work *remotely* and communicate via online tools *Requirements: * * Proven experience in one or more of the tools/areas listed above * Abili...

I have a digital down converter that decimates by 2 in VHDL for my final degree project, i compare the output with matlab fixpoint i am not able to get error zero,i guess the problem is the filter_semi_par architecture that doesnt work good,i need someone to check it and help me,the principal project is ddc_semi_par the other project is for debbug alone better if you want it the filter_semi_par architecture You’ll find a ZIP in the repository that contains: • the full project scripts and codes , • a clean, stand-alone version of the semiparallel module for faster iteration, • a small testbench that compares fixed-point results against the float-point reference. What I need from you is a precise, reproducible fix: 1. Identify why the semiparallel implem...

...runs on an Artix-7 FPGA and lets me capture analog signals up to about 50 MHz from 6 x AD9226 12 bit ADC's simultaneously . The goal is simple: store every sample intact to DDR3 for 500ms, and make the stored data available later by QSPI at 40MHz, or USART. Use one digital input as trigger to start AQ, one to erase full DDR3, one to select QSPI or USART. Scope of work • Build the RTL (VHDL or Verilog—your choice) that interfaces the FPGA with a suitable high-speed ADC, brings the samples into the fabric, and buffers them without loss. • Implement a storage path—on-chip BRAM, external DDR3—to hold the data until I pull it off the board. • Provide a clean, documented interface (for example QSPI, UART, USB FIFO) that I can use from...

I'm finishing my TFG on FPGA implementation, I need someone to help me with the semi-parallel architecture of a filter bank, I have the code done and the design scheme, but I need someone to review it and help me debug it if necessary, I can send you the files so you can take a look, thanks!

Hello, I'm Sergio, an electronic engineering student. I'm currently finishing my final degree project, which involves the implementation of several architectures, and I need help with the implementation of the parallel architecture. I need a single DSP cell to perform multiple coefficient multiplications,...be managed using SRLFIFOs with random access. I have almost all the code completed, except for the FIFOs and some debugging. I also need the design verification to be done using a MATLAB script to ensure bit-accurate results. Please review the documentation and files I have uploaded to make sure this can be donei need to deliver. You will have to edit my VHDL code and my matlab scripts to depurate the design, and the end i need the VHDL code an the matlab scri...

I'm finishing my TFG on FPGA implementation, I need someone to help me with the semi-parallel architecture of a filter bank, I have the code done and the design scheme, but I need someone to review it and help me debug it if necessary, I can send you the files so you can take a look, thanks!

...sketches the architecture (parallel engines, expected clock, resource use), names the FPGA family you would prototype on, and projects the ASIC performance and die size. Include milestones, cost and a timeline that lets us enter hardware testing within one month. Prior crypto-acceleration or high-speed ECC work is highly relevant, so highlight it briefly. Deliverables 1. Synthesizable RTL (Verilog or VHDL) covering ECC, hashing and filter logic 2. Reference bitstream for the chosen evaluation board plus host-side control script 3. Testbench & vectors proving functional correctness against VanitySearch outputs 4. Performance/power report demonstrating that the design meets or exceeds the stated targets I’m ready to start immediately and will respond ...

I need a complete, synthesizable SystemVerilog design that turns an off-the-shelf FPGA into a real-time image-processing engine. The pipeline must handle three stages—image filtering, edge detection, and object detection—culminating in an on-device CNN that...(preferably from the year 2025) for guidance or inspiration. (Focus on novelty, performance (speed, resource usage), and application relevance.) • After completing the work, I aim to publish the results in a Science Citation Index Expanded (SCIE) journal. • Give me dummy Word document, respective results in zip file etc. • Finally explain and guide me. Use any FPGA Image processing 1.Verilog HDL+ System Verilog (ML+AI+CNN etc.) : Image processing whatever Verify with FPGA board.

I’m expanding an FPGA project and need someone who can move comfortably between VHDL development and quick-turn Python scripting. On the FPGA side, the immediate task is to write, tidy up, and document VHDL modules, then verify them in simulation and on hardware. Alongside that, I’d like lightweight Python utilities to automate synthesis runs, manage bitstream builds, and trigger scripted tests so I can iterate without manual intervention. You’ll be handed my current repo (Vivado-based, with ModelSim testbenches) plus a short list of new features. From there I expect: • well-structured VHDL that meets timing in a mid-range Xilinx device • Python scripts (Python 3) that call the usual vendor CLI tools, gather logs, and flag errors automat...

I need assistance with a college project to design a Multi-Protocol Conversion Unit (MPCU) using Verilog HDL. The MPCU should convert data between SPI, I2C, and UART protocols. Requirements: - Verilog implementation for SPI, I2C, UART (both master and slave) - Top-level MPCU module to connect all protocols - Simulation testbenches and waveforms - Final report detailing design and results Tools: Xilinx Vivado or equivalent Ideal Skills: - Proficiency in Verilog HDL and digital design - Experience with FPGA tools (Vivado/ModelSim/Quartus) - Solid understanding of SPI, I2C, UART protocols Note: Academic project; only Indian freelancers

FPGA-Based Image Processing Project Objective: To design and implement a novel FPGA-based image processing system using a combination of hardware description languages, machine learning techniques, and simulation tools. The final goal is to publish the resu...(preferably from the year 2025) for guidance or inspiration. (Focus on novelty, performance (speed, resource usage), and application relevance.) • After completing the work, I aim to publish the results in a Science Citation Index Expanded (SCIE) journal. • Give me dummy Word document, respective results in zip file etc. • Finally explain and guide me. Use any FPGA Image processing 1.Verilog HDL+ System Verilog (ML+AI+CNN etc.) : Image processing whatever Verify with FPGA board.

...the missing piece is a working RTL design that is also demonstrable through Xilinx High-Level Synthesis. I already know the target platform will be a Xilinx FPGA, but I haven’t committed to a specific family yet, so you can recommend the most suitable Spartan, Virtex, or Zynq device once we look at resource needs and cost. Here’s what I still need: • A clean, synthesizable RTL description (Verilog or VHDL—whichever fits best) • A matching HLS model in C/C++ that produces equivalent results through Vivado HLS • Simulation, synthesis, and timing reports generated in the current Vivado toolchain • A concise technical note that maps the HLS code to the hand-written RTL, explains any optimizations, and gives step-by-step build instru...

I'm seeking an experienced hardware designer to assist with an ASIC project focused on front-end design. Key areas of assistance: - RTL Coding - Synthesis I have partial specifications and documentation available. Ideal skills and experience: - Proficiency in VHDL and Verilog - Strong background in ASIC design processes - Experience with RTL coding and synthesis - Ability to work with partial documentation and fill in gaps as needed. Depending on your expertise, I will offer a long-term project. Looking forward to your expertise to bring this project to fruition.

The task includes the design, VHDL-based implementation, testing, and analysis of a system as described below. You should discuss the detailed procedure of each task and critically evaluate all the results. Need to design a timer circuit which measures how fast a human hand can respond after a person sees a visual stimulus. This circuit operates as follows: 1. The circuit has three input pushbuttons, corresponding to the clear, start, and stop signals. It uses a single discrete LED as the visual stimulus and displays relevant information on the seven-segment LED display. 2. A user pushes the clear button to force the circuit returning to the initial state, in which the seven-segment LED shows a welcome message, “HI”, and the stimulus LED is off. 3. When ready, the use...

I need help setting up and running some Verilog code on an Intel FPGA. My primary requirement is assistance with setting up the development environment using Intel Quartus Prime. Key Requirements: - Expertise in setting up Verilog projects for Intel FPGAs - Proficiency in using Intel Quartus Prime for development - Ability to guide through the installation and configuration process Ideal Skills and Experience: - Strong background in Verilog programming - Experience with Intel Quartus Prime software - Familiarity with FPGA development and deployment processes - Good communication skills to provide clear guidance and support I'm looking forward to working with someone who can help streamline the setup process and ensure the code runs smoothly on the FPGA.

...seeking a knowledgeable consultant to assist in developing code for the AMD U45N FPGA using the OpenNIC framework, available on GitHub. The primary goal is to design the framework, focusing on Vivado, OpenNIC, and Verilog. This is an hourly consulting project. Key Requirements: - Develop and design framework code for AMD U45N FPGA - Utilize Vivado, OpenNIC, and Verilog in the development process - Ensure seamless integration and functionality within the framework Ideal Skills and Experience: - Strong experience with AMD FPGA development - Proficiency in Vivado, OpenNIC, and Verilog - Background in FPGA framework design and architecture - Ability to work collaboratively on an hourly consulting basis If you have the expertise in these areas and are interested in co...

I need a software-based VHDL code for switch debouncing on a Cyclone FPGA. The purpose is to eliminate noise from mechanical switches, push buttons, or toggle switches. Requirements: - VHDL code implementation - Compatible with Cyclone FPGA - Effective debouncing for mechanical switches, push buttons, or toggle switches Ideal Skills and Experience: - Proficiency in VHDL - Experience with Cyclone FPGA series - Knowledge of switch debouncing techniques

I'm seeking assistance with debugging the Ethernet transmission logic on my TANG nano 20K FPGA board, which is connected to a Hanrun HR961160C module featuring the WIZnet W5500 chip. I am attempting to send an ARP request to my laptop via an Ethernet cable, but I am not receiving any packets. I have the code available and need a detailed code review and correction. Key Requirements: - Review and correct the Ethernet transmission logic in the provided code. - Ensure proper configuration and operation of the W5500 chip. - Identify and resolve any issues preventing successful ARP request transmission. Ideal Skills and Experience: - Strong understanding of FPGA programming and Ethernet protocols. - Experience with the WIZnet W5500 Ethernet chip. - Proficiency in debugging and correcting...

I'm seeking an experienced FPGA developer to implement signal processing for communication systems. The primary task involves programming on an FPGA for on-off keying (OOK) with a custom data stream. The key requirement will be the simultaneous measurement of 8 ADC signals and aggregat... where remote access to the board can be provided. Key Requirements: - Develop and optimize signal processing algorithms for OOK - Custom data stream integration - FPGA programming expertise, preferably with Ultrascale architecture Ideal Skills: - Strong background in FPGA development - Experience with communication protocols, especially OOK - Proficient in hardware description languages (VHDL/Verilog) - Knowledge of signal processing techniques and algorithms Please share relevant ex...

I need help designing an FPGA to implement the SHA-3 hash function using the AXI4-Lite interface on a PYNQ-Z2 board. Key requirements: - Design and implement SHA-3 hash function on FPGA - Integrate design with AXI4-Lite interface - Deploy on PYNQ-Z2 board Ideal skills and experience: - Strong FPGA design expertise - Experience with crypto...function using the AXI4-Lite interface on a PYNQ-Z2 board. Key requirements: - Design and implement SHA-3 hash function on FPGA - Integrate design with AXI4-Lite interface - Deploy on PYNQ-Z2 board Ideal skills and experience: - Strong FPGA design expertise - Experience with cryptographic algorithms, particularly SHA-3 - Proficiency in AXI4-Lite interface and PYNQ-Z2 platform - Knowledge of VHDL/Verilog Please provide relevant experie...

I am seek...experienced software architect to assist in developing detailed specifications and documentation for a modular EDA (Electronic Design Automation) tool aimed at semiconductor development. The system will support both SaaS-based services and standalone products. Key deliverables include: - Interface specifications for modular components - Functional division of modules (UI design, analysis tools, Verilog parser, project management functions, etc.) - Connection specifications to ensure seamless integration between modules - Detailed documentation to guide future implementation The goal is to create a robust architecture that supports scalability and prevents duplication or external leakage. This is the first step in a multi-phase project that will include implementation an...

...with PCILeech + Screamer Squirrel bitstreams Rapid delivery and responsive support Ideal Developer Has: Extensive experience in FPGA development (especially Xilinx 7-Series) Deep knowledge of PCIe protocol, device enumeration, and configspace Prior work with PCILeech, DMA tools, or custom bitstream development Ability to implement stealthy and undetectable firmware design Proficiency in Verilog, VHDL, and possibly some embedded C Experience with anti-reverse engineering or obfuscation techniques is a bonus Timeline & Budget: Timeline is flexible — quality and performance are the priorities. Budget is open — please provide a detailed quote and portfolio/examples of similar work. If you're confident in building robust, stealth-grade PCIe emula...

...com/self-evaluation (O-1 visa section). Exceptional scores required in research impact and innovation. Confidential submissions accepted. Budget: £325,000 GBP (plus equity stake in resulting company and IP royalties) Skills Required: Neuromorphic Engineering, VLSI Design, Neuroscience, Signal Processing, Machine Learning (PyTorch/TensorFlow), Real-time Systems, C/C++, Python, MATLAB, FPGA Programming (Verilog/VHDL), Medical Device Development, Clinical Trial Design, FDA Regulatory, Patent Development, Neural Data Analysis, Brain-Computer Interfaces...

FPGA/VHDL Designer, Junior and Senior Profiles We're looking to grow our engineering team with skilled VHDL/FPGA designers for exciting ongoing and upcoming projects. Whether you're starting your journey or are a seasoned FPGA expert, we have multiple roles open. Available Roles Junior VHDL Designer(<10 years) You will receive detailed specifications. Your tasks: implement the design in VHDL, test in simulation, and document the module. Senior FPGA Designer(>10 years) Full ownership of FPGA development. From specs to integration and testing on hardware (remote). Includes VHDL coding, simulation, testbench development, and documentation. Key Responsibilities Develop and implement VHDL code for FPGA or SoC platforms. Simulate, verif...

FPGA/VHDL Designer, Junior and Senior Profiles We're looking to grow our engineering team with skilled VHDL/FPGA designers for exciting ongoing and upcoming projects. Whether you're starting your journey or are a seasoned FPGA expert, we have multiple roles open. Available Roles Junior VHDL Designer(<10 years) You will receive detailed specifications. Your tasks: implement the design in VHDL, test in simulation, and document the module. Senior FPGA Designer(>10 years) Full ownership of FPGA development. From specs to integration and testing on hardware (remote). Includes VHDL coding, simulation, testbench development, and documentation. Key Responsibilities Develop and implement VHDL code for FPGA or SoC platforms. Simulate, verif...

Description: I’m looking for a developer with experience in PCIe devices, Verilog/VHDL, or FPGA development to create a minimal, custom PCIe firmware image that emulates a specific real-world PCI device (Sound Blaster Audigy FX – SB1570). The goal is to produce a spoofed device that behaves realistically enough to: Match the real device's PCI config space Load the official Windows driver without issue Pass enumeration and capability checks handle basic MMIO reads/writes I can provide: A full PCI config space dump (Vendor ID, Device ID, Class, BARs, capabilities) A sample MMIO register map Known-good layout for capability chains Reference BAR sizes and expected stub values You will: Implement device_config.v or equivalent Build mmio_handler.v with...