Verilog / VHDL Роботи та конкурси

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Проект/Конкурс Описання Заявки/Роботи Навички Розпочато Закінчується Ціна (USD)
communication using simulink blocks update file of one user to five user 7 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 12, 2017 Сьогодні6д. 13г. $137
robust control project design a control system using matlab or simulink 14 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 12, 2017 Сьогодні6д. 8г. $47
model in simulink i have model for one user i want update to 5 user and get some results 10 Техніка, Matlab and Mathematica, Verilog / VHDL, Технологія машинобудування, Електротехніка Dec 12, 2017 Сьогодні6д. 7г. $375
calculate speed between two points in verilog im making missile command and i have (x1,y1) and (x2,y2). how can I calculate the x step and y step values? 7 Verilog / VHDL Dec 12, 2017 Dec 12, 20175д. 23г. $35
Finite State machine for washing machine FPGA We need an expert of FPGA for fsm of washing machine analysis and synthesizes 5 Електроніка, Verilog / VHDL, Мікроконтролер, Електротехніка, FPGA Dec 12, 2017 Dec 12, 20175д. 20г. $94
little project about emitter follower (manually and simulated) -- 2 - 11/12/2017 21:32 EST Help me to design the circuit attatched and find out the unkown parameters both 10 Техніка, Електроніка, Verilog / VHDL, Мікроконтролер, Електротехніка Dec 11, 2017 Dec 11, 20175д. 17г. $32
Analogue & Digital Electronic Please, see the attached file. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 16 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 11, 2017 Dec 11, 20175д. 11г. $207
multisim function generator hi i want someone to connect the function generator and the scope in multisim of electric circuit thank you 9 Техніка, Електроніка, Verilog / VHDL, Електротехніка, Схемотехніка Dec 11, 2017 Dec 11, 20175д. 11г. $23
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка, FPGA Dec 11, 2017 Dec 11, 20175д. 5г. $23
Microprocessor Project using CodeWarrior Software Hi, Need the completed project in 36 hours. Share the codes in 24 hours and the report in 36 hours. Project details are attached here. Sample codes are attached in the files. You need to use the similar codes for the work 3 Техніка, Електроніка, Verilog / VHDL, Мікроконтролер, Електротехніка Dec 11, 2017 Dec 11, 20174д. 22г. $100
VHDL to Verilog Translation I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language. 9 Verilog / VHDL Dec 10, 2017 Dec 10, 20174д. 16г. $120
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Техніка, Електроніка, Verilog / VHDL, Електротехніка, FPGA Dec 9, 2017 Dec 9, 20172д. 22г. $55
System verilog Verification Project Plz contact me. I have other code for it as well. You will just need to restructure the code and it should be good enough. 12 Техніка, Електроніка, Verilog / VHDL, Електротехніка, FPGA Dec 9, 2017 Dec 9, 20172д. 21г. $26
simulation/ VHDL Expert Needed -- Urgent job -- 3 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 3 Техніка, Електроніка, Verilog / VHDL, Електротехніка Dec 9, 2017 Dec 9, 20172д. 21г. $45
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Техніка, Електроніка, Verilog / VHDL, Електротехніка Dec 9, 2017 Dec 9, 20172д. 21г. $35
simulation/ VHDL Expert Needed -- Urgent job -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Техніка, Електроніка, Verilog / VHDL, Електротехніка Dec 9, 2017 Dec 9, 20172д. 21г. $35
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 Техніка, Електроніка, Verilog / VHDL, Електротехніка, FPGA Dec 9, 2017 Dec 9, 20172д. 21г. -
simulation/ VHDL Expert Needed -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 4 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 9, 2017 Dec 9, 20172д. 21г. $34
simulation/ VHDL Expert Needed I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 9, 2017 Dec 9, 20172д. 21г. $38
Electronics Engineer/Tutor Hi, I am looking for a Electronics Engineer/Tutor who can tutor me some important concepts of the Engineering Design. I am looking for someone who has background in Electronics and Digital Logic Design. Happy Bidding! 20 Техніка, Електроніка, Verilog / VHDL, Електротехніка Dec 8, 2017 Dec 8, 20172д. 18г. $12
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 10 Електроніка, Verilog / VHDL, Мікроконтролер, Електротехніка, FPGA Dec 8, 2017 Dec 8, 20171д. 20г. $439
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab and Mathematica, Verilog / VHDL, Електротехніка, FPGA Dec 7, 2017 Dec 7, 20171д. 18г. $783
Digital Logic Circuit using Logisim Hello, I am looking to build a circuit in Logisim that requires digital logic expertise. Project description will be provided upon contact. Computer science backgrounds, circuit design, and digital logic expertise required (preferably using Logisim). 21 Техніка, Електроніка, Verilog / VHDL, Електротехніка, Цифровий дизайн Dec 6, 2017 Dec 6, 201710г. 21х. $87
need help with missile command game on de2-115 does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files. 4 Verilog / VHDL Dec 5, 2017 Dec 5, 2017Закінчився $127
micro controller need somebody good in micro controller and has ever coded using vhdl 18 Програмування на С, Verilog / VHDL, Мікроконтролер, Електротехніка, FPGA Dec 5, 2017 Dec 5, 2017Закінчився $174
Expert in Xilinx (VHDL-BASED) An efficient Glitch power reduction using sequential clock gating in VLSI circuits 8 Verilog / VHDL Dec 5, 2017 Dec 5, 2017Закінчився $162
Project for SqUa11 -- 2 3x3 Systolic array matrix using rom and ram 2 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка, Dec 4, 2017 Dec 4, 20171д. 18г. $12
Embedded systems Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the... 9 Електроніка, Verilog / VHDL, Мікроконтролер, Архітектура ПЗ, Arduino Dec 4, 2017 Dec 4, 2017Закінчився $42
Implementation of 32-bit MIPS Processor I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project. 7 Програмування на С, Verilog / VHDL, Архітектура ПЗ, Асемблювання, x86/x64 Assembler Dec 4, 2017 Dec 4, 2017Закінчився $117
Write an article about UVM (universal verification methodology) Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM. The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? " The article needed to be original and meaningful content. Please bid with your experience in ASIC ver... 26 Verilog / VHDL, Розробка технічних документів Dec 4, 2017 Dec 4, 2017Закінчився $98
putty language i need someone who can do putty and verilog 7 Техніка, Verilog / VHDL, Електротехніка, Асемблювання Dec 4, 2017 Dec 4, 2017Закінчився $111
Verilog Work I need some work done in verilog using Quartus 2 version 13 12 Verilog / VHDL Dec 3, 2017 Dec 3, 2017Закінчився $145
putty coding language need an electrical engineer or computer engineer with background in putty language coding 3 Verilog / VHDL, Електротехніка, Кодування, Програмування Dec 3, 2017 Dec 3, 2017Закінчився $28
Need a Cadence design to design a amplifier circuit. Need a Cadence design to design a amplifier circuit. details will be share in chat box. 21 Техніка, Електроніка, Verilog / VHDL, Електротехніка, Схемотехніка Dec 3, 2017 Dec 3, 2017Закінчився $25
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 Техніка, Електроніка, Verilog / VHDL, Схемотехніка, FPGA Dec 2, 2017 Dec 2, 2017Закінчився $45
MATLAB code- a bit-serial CORDIC computer in Verilog MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later 15 Matlab and Mathematica, Verilog / VHDL Dec 2, 2017 Dec 2, 2017Закінчився $62
Digital Design with Logic Devices It is a Project on Digital Design with Programmable Logic Devices. I will provide details later. 10 Verilog / VHDL Dec 1, 2017 Dec 1, 2017Закінчився $52
pls help ac homewokr :'( i need log synchronous sequential circuit that solves a 64x64 maze using the right wall follower algorithm. how much???? u have 3 hours 8 Техніка, Електроніка, Matlab and Mathematica, Verilog / VHDL, Електротехніка Dec 1, 2017 Dec 1, 2017Закінчився $83
Project for Gabriel G. Hi Gabriel! I'm working on my capsim simulation final and I got myself into a lot of debt and don't know how to fix it . I need a 70% on this and was wondering if you'd be able to help. Im currently on the 3rd round of 4. Would you be able to help me out? You were suggested by a classmate and was wondering if you'd be able to help me even though I already am on round 3. Thank... 2 Управління проектом, Телемаркетинг, Excel, Matlab and Mathematica, Verilog / VHDL, Dec 1, 2017 Dec 1, 2017Закінчився $147
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 Програмування на С, Verilog / VHDL, Програмування на C++, Асемблювання, FPGA Nov 30, 2017 Nov 30, 2017Закінчився $157
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017Закінчився $83
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 Програмування на С, Техніка, Verilog / VHDL, FPGA, Parallel Processing Nov 29, 2017 Nov 29, 2017Закінчився $172
logic analyiser and waveform viewer The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microproce... 6 Електроніка, Verilog / VHDL, Мікроконтролер, Архітектура ПЗ, Arduino Nov 27, 2017 Nov 27, 2017Закінчився $322
interface hardware module with amber processor -- 2 - 27/11/2017 11:51 EST to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 27, 2017 Nov 27, 2017Закінчився $211
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 Техніка, Verilog / VHDL, Електротехніка, Адміністрування мережі, FPGA Nov 26, 2017 Nov 26, 2017Закінчився $675
C++ based project - open to bidding cpp dependencies sorting out, we will provide you the structured file and the source code and you have to compile and run after sorting mugs from that 16 Електроніка, Verilog / VHDL, Програмування на C++, Arduino, RTOS Nov 25, 2017 Nov 25, 2017Закінчився $108
Design and test a VHDL model for the instruction cache of a speculative out of order VLIW processor. Design and test a VHDL model for the instruction cache of a speculative out-of-order VLIW processor. Your VHDL code should have the following: - PC register updated on falling_edge of the clk to one of the following values: PC + VLIW_INST_SIZE, branch_target_PC, or EXCEPTION_ROUTINE_PC. PC register should be initialized to 1000 Hex when reset is active. Assume that the project ISA requires EXCE... 3 Verilog / VHDL Nov 25, 2017 Nov 25, 2017Закінчився $361
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 Програмування на С, Verilog / VHDL, Програмування на C#, Програмування на C++, FPGA Nov 23, 2017 Nov 23, 2017Закінчився $11
interface hardware module with amber processor to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 23, 2017 Nov 23, 2017Закінчився $30
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 Програмування на С, Verilog / VHDL, Програмування на C++, Асемблювання, FPGA Nov 23, 2017 Nov 23, 2017Закінчився $10
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