Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Найняти Verilog / VHDL Designers

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    15 робіт знайдено, ціни вказані в USD
    Find FPGA expert - pin assignment 6 дні(-в) left
    ПІДТВЕРДЖЕНО

    Looking for expert on FPGA - 192 pins assignment on 10M16D324C8G FPGA

    $163 (Avg Bid)
    $163 Сер. заявка
    4 заявки
    IoT expert needed 6 дні(-в) left
    ПІДТВЕРДЖЕНО

    I need to simulate routing protocols using Ns2 or ns3 [увійдіть, щоб побачити URL] Request details protocols used are AODV and Fuzzy logic Deliverables Source code and results with graphs also datasets , all requirements will be submitted , protocols used are AODV and Fuzzy logic

    $140 (Avg Bid)
    $140 Сер. заявка
    4 заявки
    Microcontroller 5 дні(-в) left
    ПІДТВЕРДЖЕНО

    using MPLAB software and expert in microcontroller

    $36 (Avg Bid)
    $36 Сер. заявка
    13 заявки
    Expert in RISC V Programming (MIPS) -- 2 5 дні(-в) left
    ПІДТВЕРДЖЕНО

    I am looking for an expert in RISC V programming, also Neural Network, Assembly, MIPS

    $226 (Avg Bid)
    $226 Сер. заявка
    3 заявки
    Expert in RISC V Programming (MIPS) 5 дні(-в) left
    ПІДТВЕРДЖЕНО

    I am looking for an expert in RISC V programming, also Neural Network, Assembly, MIPS

    $352 (Avg Bid)
    $352 Сер. заявка
    5 заявки
    Should be familiar with cadeance nclaunch 4 дні(-в) left
    ПІДТВЕРДЖЕНО

    To write the code in gedit and simulate the same In cadeance and didign vision

    $135 (Avg Bid)
    $135 Сер. заявка
    2 заявки

    Development of software modules for overlapping windowed 4096 point FFT computation for spectrum analysis of the two analog signals. It should compute minimum 4096 point FFT simultaneously for each of the two vibration signals. The FFT computation shall be done for 500 ms of data with an update rate of 100ms and overlap of 400 ms.

    $127 (Avg Bid)
    $127 Сер. заявка
    8 заявки
    8263_Verilog Developer Needed 2 дні(-в) left
    ПІДТВЕРДЖЕНО

    A reliability enhanced video storage architecture in hybrid SLC/MLC NAND flash memory

    $250 (Avg Bid)
    $250 Сер. заявка
    1 заявки
    RF project for AM receiver -- 2 1 день left
    ПІДТВЕРДЖЕНО

    Design An AM/SSB/CW receiver (uses product detector) capable of receiving signals (tunable) within the 6m Amateur Radio band (50 to 54 MHz). Input sensitivity 10 dB SINAD at -90 dBm. System should include electronic AGC dynamic range of at least 30 dB, and capability of 20 dB of manually selectable input signal attenuation. Output must drive an 8-ohm speaker and be capable of at least 100 mW of au...

    $497 (Avg Bid)
    $497 Сер. заявка
    11 заявки
    50-54 MHz Tunable AM Receiver Driving an 8 Ohm Speaker -- 4 1 день left
    ПІДТВЕРДЖЕНО

    Design An AM/SSB/CW receiver (uses product detector) capable of receiving signals (tunable) within the 6m Amateur Radio band (50 to 54 MHz). Input sensitivity 10 dB SINAD at -90 dBm. System should include electronic AGC dynamic range of at least 30 dB, and capability of 20 dB of manually selectable input signal attenuation. Output must drive an 8-ohm speaker and be capable of at least 100 mW of au...

    $511 (Avg Bid)
    $511 Сер. заявка
    7 заявки
    Vhdl code for radix comparator 23 годин(-и) left
    ПІДТВЕРДЖЕНО

    Its basically writing code in Vhdl and simulate the same in edit & and cadeance nclaunc &

    $32 (Avg Bid)
    $32 Сер. заявка
    5 заявки
    Verilog/VHDL -2 17 годин(-и) left
    ПІДТВЕРДЖЕНО

    Verilog Please solve as beginner and can you please provide the explanation of the code Deadline : 3 days ( 72 hours )

    $14 - $34
    Прихований
    $14 - $34
    18 заявки
    Verilog/VHDL -1 17 годин(-и) left
    ПІДТВЕРДЖЕНО

    Verilog Please solve as beginner and can you please provide the explanation of the code Deadline : 4 days ( 96 hours )

    $20 - $47
    Прихований
    $20 - $47
    19 заявки
    Powerworld Simulator 11 годин(-и) left

    I need to know if any experts on Powerworld Simulator are available who can assist me learning and executing power system fault calculations in Powerworld Simulator.

    $13 / hr (Avg Bid)
    $13 / hr Сер. заявка
    13 заявки

    Будь ласка, зареєструйтесь або увійдіть в систему для перегляду деталей.

    Прихований Угода про нерозголошення