Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Найняти Verilog / VHDL Designers

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    17 робіт знайдено, ціни вказані в USD
    Intel Quartus Mealy and Moore machine circuit design for project 6 дні(-в) left
    ПІДТВЕРДЖЕНО

    finite-state synchronous machines mealy and moore machine for given task, using Intel Quartus.

    $181 (Avg Bid)
    $181 Сер. заявка
    15 заявки

    Hello, I need to create a project in VHDL: a simple operations calculator (addition, subtraction, multiplication, and division). The result have to be displayed on the PmodCLP I need this to implement on the board NEXYS 4, Artix 7 FPGA. The VHDL code should be developed in Xilinx ISE. I would need the documentation. Also include as many comments as you can about what is going on so that I can...

    $210 (Avg Bid)
    $210 Сер. заявка
    3 заявки

    Hello, I need to create a project in VHDL: a simple operations calculator (addition, subtraction, multiplication, and division). The result have to be displayed on the PmodCLP I need this to implement on the board NEXYS 4, Artix 7 FPGA. The VHDL code should be developed in Xilinx ISE. I would need the documentation. Also include as many comments as you can about what is going on so that I can...

    $240 (Avg Bid)
    $240 Сер. заявка
    6 заявки
    Design Verification 5 дні(-в) left

    PCle, ethernet , UVM, System Verilog

    $200 (Avg Bid)
    $200 Сер. заявка
    2 заявки
    Custom Camera Software 4 дні(-в) left

    We plan to use the Sny IMX420 imager, the Framos IP Core and a Xilinx FPGA. Looking for a vision software freelancer with experience in these technologies. Vivado 2018 or later.

    $52 / hr (Avg Bid)
    $52 / hr Сер. заявка
    9 заявки
    Simulating Multiple Gates - Third installment (Verilog + C) 4 дні(-в) left
    ПІДТВЕРДЖЕНО

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $63 (Avg Bid)
    $63 Сер. заявка
    10 заявки
    Make an interface for a MIPS Game 3 дні(-в) left
    ПІДТВЕРДЖЕНО

    *CHEAPEST BID WILL WIN* I need someone to code an interface for a game similar to minesweeper in MIPS. The logic and everything is provided, all I need someone is to complete the interface. This sounds very complicated but it's an easy job, and that's why this comes under micro project. Files and more details will be provided over chat.

    $43 (Avg Bid)
    $43 Сер. заявка
    3 заявки
    Project in system verilog 3 дні(-в) left
    ПІДТВЕРДЖЕНО

    Build a project using system verilog

    $198 (Avg Bid)
    $198 Сер. заявка
    10 заявки
    CSE/EEE Micro-controller Application 2 дні(-в) left
    ПІДТВЕРДЖЕНО

    Micro-controoler Application on Terasic DE10-Lite, FPGA board

    $36 (Avg Bid)
    $36 Сер. заявка
    4 заявки
    Finite state machine using Quartus 2 дні(-в) left
    ПІДТВЕРДЖЕНО

    finite-state synchronous machines mealy and moore machine for given task.

    $133 (Avg Bid)
    $133 Сер. заявка
    21 заявки
    Work on VHDL Laboratory like Latches, Flip-flops and registers 2 дні(-в) left
    ПІДТВЕРДЖЕНО

    Need to investigate the latches, flip-flops and the registers in VHDL laboratory work

    $67 (Avg Bid)
    $67 Сер. заявка
    9 заявки

    digital Alarm clock. I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

    $56 (Avg Bid)
    $56 Сер. заявка
    10 заявки

    I need it for my final project. Please let me know if anyone can do it in 20$. Lowest bit will be rewarded.

    $28 (Avg Bid)
    $28 Сер. заявка
    7 заявки

    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus.

    $15 (Avg Bid)
    $15 Сер. заявка
    2 заявки
    Simulating Multiple Gates third installment c + verilog 1 день left
    ПІДТВЕРДЖЕНО

    The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third ins...

    $50 (Avg Bid)
    $50 Сер. заявка
    16 заявки
    OFDM Waveform Development 23 годин(-и) left
    ПІДТВЕРДЖЕНО

    Need someone to develop OFDM waveform on AD9361 or any other transceiver and FPGA.

    $1225 (Avg Bid)
    $1225 Сер. заявка
    10 заявки
    Digital Logic Project 12 годин(-и) left
    ПІДТВЕРДЖЕНО

    hello, please if you can comment out the verilog code and the steps done, so we know how to explain it. also, i need this project to be done in exactly one week from today. thank you

    $49 (Avg Bid)
    $49 Сер. заявка
    8 заявки