Assembly language program

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Details: The purpose of this project is to help solidify your understanding of the details of how caches and memory work by building a multi-level cache and memory model that processes address traces concurrently on a dual-core CPU. Your caches must support several design options and be configurable. For example, your cache simulator should support different sizes (number of entries), different cache line sizes, and different levels of associativity as described in the following sections. You will need to maintain hit/miss ratio statistics as well as a running average of instruction latencies during execution that will be aggregated into reportable performance metrics upon completion of address trace processing.

I will send detail if you are able to do it.

Budget 75$

Deadline March 17

Асемблювання Архітектура ПЗ Тестування ПЗ x86/x64 Assembler

ID Проекту: #7260747

Про проект

2 заявок(-ки) Дистанційний проект Остання активність Apr 12, 2015

2 фрілансерів(-и) готові виконати цю роботу у середньому за $112

kandamunlabs

Hello, I have used a few cache simulation tools, but I have never made my own simulator. I might be able to do this project. Please provide more details.

$99 USD за 7 дні(-в)
(43 відгуків(и))
5.3
dinhks

Hi I am Dinh. Hope to work with you. >>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>>>>>>>>>

$125 USD за 3 дні(-в)
(12 відгуків(и))
3.7