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design with Altera FPGA

4 фрілансерів(-и) готові виконати цю роботу у середньому за £232

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Більше

£250 GBP за 3 дні(-в)
(89 відгуків(и))
6.4
Softeria

I am Electronics Engineer. My Expertise are MATLAB, Simulink, AUTO CAD, Pro E, Verilog, Python, PSSE, PWS, PSS Sincal, ORCAD, Altium(PCB design pursuit) ,MPLAB, Xilinx (VHDL, HDL). PLC, SCADA Systems, Wireshark and pac Більше

£150 GBP за 3 дні(-в)
(5 відгуків(и))
4.1
tienthanhkt09

Hi there, I have experienced in VHDL design and Timing closure analysis. I also familiar with Xilinx and Intel tools design. please take a look via my profile. thanks.

£277 GBP за 4 дні(-в)
(0 відгуків(и))
0.0
asicdsm

I can compile with Precision RTL and/or Synplify. Do you have the constraints defined in plain text ?

£250 GBP за 1 день
(0 відгуків(и))
0.0