Front End VLSI Design engineer Part Time in Bangalore
Looking for expert FPGA Design engineer with RTL Design [Verilog]
Proven track record of designing, developing, prototyping, and testing high speed FPGA designs
Experience in Verilog programming & experience with Xilinx devices and development tools
Design Simulation experience [Modelsim]
Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.
12 фрілансерів(-и) у середньому готові виконати цю роботу за ₹12794
Hi, I have done my Mtech in VLSI design. I had also done my thesis on FPGA implementation of multiplier using verilog on Xillinx. please give me one chance.