Закрито

VLSI Design Engineer - Part Time

Front End VLSI Design engineer Part Time in Bangalore

Looking for expert FPGA Design engineer with RTL Design [Verilog]

Proven track record of designing, developing, prototyping, and testing high speed FPGA designs

Experience in Verilog programming & experience with Xilinx devices and development tools

Design Simulation experience [Modelsim]

Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.

Навички: Електроніка, FPGA, Verilog / VHDL

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Про роботодавця:
( 0 відгуки(-ів) ) Bengaluru, India

ID Проекту: #17806356

12 фрілансерів(-и) у середньому готові виконати цю роботу за ₹12794

raulbehl

Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.

₹12500 INR за 7 дні(-в)
(57 відгуків(и))
5.8
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Більше

₹13888 INR за 3 дні(-в)
(72 відгуків(и))
6.1
vlsirajagopal

having good experience in verilog design and verification. Did many projects on xilinx FPGA. I can do this well.

₹7777 INR за 3 дні(-в)
(16 відгуків(и))
5.1
hungfreelancer

Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS, modelsim, vivado FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for desig Більше

₹1500 INR за 3 дні(-в)
(2 відгуків(и))
1.7
sarathsukumar

Developers in Bangalore...….MADIVALA Embedded, VLSI ………. ...

₹50000 INR за 3 дні(-в)
(0 відгуків(и))
0.0
₹1750 INR за 6 дні(-в)
(0 відгуків(и))
0.0
kartikprmr

Hello, I have 10 years of experience in ASIC/FPGA Design & Verification. I am willing to work part time. I have expertise in following languages: Verilog VHDL Systemverilog/ UVM MATLAB Python Perl I would like to wo Більше

₹10000 INR за 7 дні(-в)
(0 відгуків(и))
0.0
prsingla19

Hi, I have done my Mtech in VLSI design. I had also done my thesis on FPGA implementation of multiplier using verilog on Xillinx. please give me one chance.

₹13888 INR за 7 дні(-в)
(0 відгуків(и))
0.0
ibnuhasan

Currently working in Qualcomm. This maybe my first project in Freelancer, so im giving you very cheap quote.

₹7777 INR за 3 дні(-в)
(0 відгуків(и))
0.0
Aaryajaya

Has 3yr of experience in RTL design and Test bench writing in VHDL/ Verilog/ System verilog . Handled many FPGA related project from RTL design( in both Verilog/VHDL) to bring up . worked on : UART,I2C,SPI,Ethernet(R Більше

₹11111 INR за 3 дні(-в)
(0 відгуків(и))
0.0
sushantk2

Hi, I can give guarantee of my work. I put 100% in my work.

₹10000 INR за 7 дні(-в)
(0 відгуків(и))
0.0
₹13333 INR за 5 дні(-в)
(0 відгуків(и))
0.0