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system verilog alarm clock and DE10-lite FPGA programming

$30-250 USD

Завершено
Опублікований over 4 years ago

$30-250 USD

Оплачується при отриманні
All code written in system verilog and the functions mod or divide not allowed Time should be displayed on the 6 digits of the seven segment displays (HHMMSS) -hours displayed in military time -when SW2=1, alarm is set and 6 digits display alarm time -when KEY0=0, the alarm is reset to 0, KEY0 takes priority over SW2 The alarm clock must be accurate, divide down the 50MHz clock at PIN_P11 as necessary on the DE10-Lite. For all frequeny dividers use a 50% duty cycle. This should be constructed similar to a counter. Switch functions: SW0=1 =reset SW1=1 =time set SW2=1 = alarm set SW3=1=set hours SW3=0=set minutes SW4=1 run clock time SW5=1 run active alarm KEY0 pressed (=0) causes alarm reset KEY1 pressed (=0) sets whatever is selected at 2 Hz clock rate The simulation verifiaction module should be: module alarm_clock(input CLK_2Hz, reset, time_set, alarm_set, sethrs1min0, run_clock, activatealarm, alarmreset, runset, output logic [7:0] sec, min, hrs, min_alarm, hrs_alarm, output logic alarm); write code for a test bench to do the following: -do a reset -set alarm to 5 hours 30 minutes -set time to 5 hours 29 minutes -activate alarm -activate run time -after alarm goes off, reset -reset clock write code for physical verification/programming of DE10-Lite module alarm_clock_pv(input CLK, SW5, SW4, SW3, SW2, SW1, SW0, KEY1, KEY0, output logic [6:0] SEC_LSB, SEC_MSB, MIN_LSB, MIN_MSB, HR_LSB, HR_MSB, output logic LED7, LED5, LED3, LED2, LED1, LED0); (module should instantiate alarm_clock module) The clock is associated with a 50MHz clock on FPGA PIN_11, and will have to be divided down to 2Hz using a frequency divider at 50% duty cycle LED functions: LEDs 0-5 turn on when corresponding switches turn on, LED7 is the alarm and should blink at a 2Hz rate until reset Button Functions: KEY0 clears alarm, KEY1 gives hours or minutes to set, depending on SW3 -only set hours and minutes so seconds should be clear when setting alarm, whenever alarm set switch is activated alarm time should be shown, default is time Seven Segment Display: write code to transform from numbers to arrays to the 7 segment displays. Will need to break numbers up into high order and low order digits and transferring them to the seven segment displays.
ID проекту: 22154312

Про проект

8 пропозицій(-ї)
Дистанційний проект
Активність 4 yrs ago

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Аватарка користувача
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done with very high difficult project in backend design in FPGA by correct timinig closure for FPGA with 400 Mhz in Virtex Ultrascale+ in some field like mining coin (bitcore, and lyra2rev3) Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.
$100 USD за 1 день
4,9 (86 відгуки(-ів))
6,7
6,7
8 фрілансерів(-и) готові виконати цю роботу у середньому за $272 USD
Аватарка користувача
Dear sir I have more than 10 years experience in in digital design using system verilog please check my profile also please message me so that we can discuss
$111 USD за 1 день
4,9 (464 відгуки(-ів))
8,0
8,0
Аватарка користувача
Hello! Please check my reviews and profile to know a bit about me and my work. It would be great if I could help you out. I already have the FPGA setup ready and should be able to work on it right away!
$160 USD за 7 дні(-в)
4,9 (81 відгуки(-ів))
6,2
6,2
Аватарка користувача
Hi, I have been working in verilog-vhdl and xilinx and altera fpgas by more than 6 years. I can complete your task in given time. Thanks.
$300 USD за 7 дні(-в)
4,8 (33 відгуки(-ів))
6,1
6,1
Аватарка користувача
Hi, I am an electronic engineer with more than 6 years of experience in system Verilog and FPGA development. I have done many complex designs including IP core development of Ethernet as well. I read your project carefully and decided to apply for the project because I have hands-on experience in Altera devices, and have done many projects based on Altera DE series boards. As for solutions, you have clearly mentioned requirements and I can straight away start development. But there are a few questions I need answers from you. When setting time, and alarm time, is it only one-way counting? or do you intend to make up and down counting with more buttons? (I am asking because I can see only one button to set hours and minutes) I can provide simulations, ALtera board verifyied source codes and Quarrtus Prime project file. Looking forward to hearing back from you. Thank you Anusha
$200 USD за 4 дні(-в)
4,9 (29 відгуки(-ів))
5,4
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Аватарка користувача
We are a team of Electrical and Electronics engineers and we are Excellent in the following areas: • Embedded C Programming. • VHDL/Verilog • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. Also we have good command over report writing, I can show you many samples of our previous reports. Kindly consider us for your project and text me so that we can further discuss specifically about your project's main goals and requirements. We can deliver your project efficiently at a time. If you choose me, I think you won't regret. Best Regards. Also we have good command over REPORT WRITING, We can show you many samples of our previous reports. We can discuss further details in the message box.
$250 USD за 7 дні(-в)
4,8 (14 відгуки(-ів))
4,9
4,9
Аватарка користувача
Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip with 16 core of 16bit MIPS such that I think I can do your task very well. Please see reviews in Verilog project which I complete very well. Best Regard.
$55 USD за 3 дні(-в)
5,0 (8 відгуки(-ів))
4,3
4,3
Аватарка користувача
Hello, I am Engineer and interested in your project. I have some questions regarding your project. Please tell me about your time limits? When you want your project to be completed? See my profile and reviews for further details. Regards Engineer Nouman
$1 000 USD за 10 дні(-в)
5,0 (1 відгук)
3,3
3,3

Про клієнта

Прапор UNITED STATES
Albany, United States
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