Create a verilog code for a logic circuit

The circuit has three 1-bit inputs A, B, C and two 1-bit outputs F and G. You are required to implement this circuit using structural verilog with hierarchical modeling. The code that is needed from you: Create two modules, one module for the circuit inside the round rectangle and a top level module that implements the complete circuit and uses the inner circuit module. Name the top level module with the same name as the file/ project name (Top-level Design Entity). Hint: Label all wires