AC/DC, DC/DC with VHDL
$30-250 USD
Оплачується при отриманні
I will not consider anything above 200$
bid and you will receive more info on the project
ID Проекту: #6626464
Про проект
20 фрілансерів(-и) готові виконати цю роботу у середньому за $249
Dear sir, I have more than 7 years experience in digital design using VHDL please give me more details about the required work
I can help you roght awaY! Please send me a message with your project! Please look at my profile! Have a nice day!
Hello sir, I am interested in more details about the project. could you contact me with more information? Regards
Hi. I am a professional Electronics Engineer having expertise in AC/DC and DC/DC converters. Contact me and have a discussion about it.
conatact me thankss ssssssssssssssssss ssssssssssssssssssssssssssssssssssssssssssssssssssss sssssssssssssssssss
Please send me details of your work. So that i can guide you better on this work. Looking forward to your positive response. Regards, Ali
I have experience in this field i developed many games and implemented research papers during last some year of experience.
I am master in vhdl and verilog. ..let me know the requirements. ..I can adjust the my deal ...try to give chance
I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Більше
My qualification is M.Tech. in VLSI and Embedded System. I have completed equalizer and text entry system project using VHDL.
I have good knowledge of electronics and of course VHDL. I can perform this job in 3 days at most. I am new in freelancer but have graduated from University in Electronics.
Hello, I have 4+ years experience in FPGA programming. I am involved in all steps of FPGA design cycle - Architecture, coding, functional simulation, timing simulation, board testing and debugging. I have worked on hi Більше
I have a good knowledge on electronic and electric, I can do a nice work just give more information about your project.
Hi, Iam asic engineer with three years of exp in RTL Design using verilog and system verilog.i designed DDR2,LPDDR2,GPIO,AHB,APB,AXI,ISO7816