Optimization of verilog codes
$30-250 USD
Оплачується при отриманні
Hi there. Could someone out there help me in optimizing my Verilog codes. I had my Verilog codes. It was made just for testbench simulation. My problem now is to implement those codes in the actual fpga board but I'm having some troubles in compiling it because it's so big. I need to reduce it to fit in my board.
ID Проекту: #6249373
Про проект
13 фрілансерів(-и) готові виконати цю роботу у середньому за $125
Hi I am having 10+ years of experience in Verilog/VHDL , I am ready to help you out in few hours please let me know when can we have team viewer session or transfer me your project. Thanks SK
dude try me as i am electronics engineer , so i do have knowledge of all electronics software.........................................lemme do....thanks
i am expert at verilog coding i can help you in this regards kindly assign me this task i can help you i shall be really thankful to you for this act
I have worked on High speed FPGA designs in Verilog, in Virtex6 FPGA, which required lots of logic optimization to meet timing requirements. I believe I can optimize your code so that it fits into your target board as Більше
i am quite sure i can do it for you in short time. let now more detail and have further discussion to solve your problem
Hi, I have enough good experience in Verilog/VHDL FPGA projects and was successful for the past 10 years.