Design Logic Circuit using VHDL

$10-30 USD

Завершено

Опублікований

over 7 years ago

$10-30 USD

Оплачується при отриманні

This project require you to design a logic circuit using state machine of ( nim game misere strategy) and implement it using VHDL. The code should be written to run on altera E2_115 board. All detail is elaborated in the attached word document. you should do the following: 1. you must include the de-bouncer VHDL file in your code as a component and use it as it is, no change is allowed inside it. (this file attached). 2. Algorithmic State Machine of the system that you used in your code and the Block diagram of The design . 3. Fully documented VHDL source code 4. Pin assignment file good luck

Verilog / VHDL

ID проекту: 12002538

Про проект

9 пропозицій(-ї)

Дистанційний проект

Активність 7 yrs ago

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Доручений:

@kulwantsingh16

$80 USD за 5 дні(-в)

4,6

(15 відгуки(-ів))

4,2

9 фрілансерів(-и) готові виконати цю роботу у середньому за $115 USD

@ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using VHDL, please check my profile, also please message me so that we can discuss

$166 USD за 2 дні(-в)

4,9

(475 відгуки(-ів))

8,1

@loi09dt1

Hello, I did this project before on DE2 board of Altera last year for a student Please contact me so that we can discuss more.

$20 USD за 1 день

4,9

(111 відгуки(-ів))

6,5

@rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency

$111 USD за 5 дні(-в)

4,9

(5 відгуки(-ів))

4,5

@SqUa11

Hello, Thanks for your invitation. My name is Mohamed. I have 5 years experience in VHDL and Verilog. I checked your project description and I can handle it. Contact me. Regards

$100 USD за 1 день

4,9

(17 відгуки(-ів))

4,1

@SANGITAR

i have over 8 years of experience programming with VHDL and Verilog .I am ready to take on the task.

$277 USD за 10 дні(-в)

5,0

(3 відгуки(-ів))

4,1

@oharwot

Hello this is complicated task requring lot of work. I can d this in high quaility with your help (board acess). Some FSM will be necessary and some AI as well. Ondrej

$222 USD за 10 дні(-в)

5,0

(5 відгуки(-ів))

2,5

@khaled93

Hi my name is Khaled i'm Electronics and communication engineer specially digital design engineer i worked before on designing digital electronics circuits and i have experience on it i worked before on designing GPU and CPU in VHDL codes as a part of my studies ,i read the file you attached and play the game on site , it's very nice game :D it motivates me to do this task

$35 USD за 5 дні(-в)