Закрито

VLSI Design Engineer - Part Time - 20/09/2018 08:19 EDT

Front End VLSI Design engineer Part Time in Bangalore

Looking for expert FPGA Design engineer with RTL Design [Verilog]

Proven track record of designing, developing, prototyping, and testing high speed FPGA designs

Experience in Verilog programming & experience with Xilinx devices and development tools

Design Simulation experience [Modelsim]

Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.

Навички: Електроніка, FPGA, Verilog / VHDL

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Про роботодавця:
( 0 відгуки(-ів) ) Bengaluru, India

ID Проекту: #17806358

4 фрілансерів(-и) у середньому готові виконати цю роботу за ₹10833

rubelsarkar161

Hi... If you need Analog/Digital layout design engineer in future please contact...

₹11111 INR за 3 дні(-в)
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2.0
₹11111 INR за 30 дні(-в)
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kartikprmr

Hello, I have expertise in ASIC/FPGA Design & Verification and worked on following languages. VHDL Verilog Systemverilog/UVM MATLAB Python Perl I am willing to work in this project as part time job. Please get back Більше

₹10000 INR за 7 дні(-в)
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₹11111 INR за 5 дні(-в)
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