Design a baseline H.264 encoder with Verilog so that it can be complied and synthesized in Xilinx or Quartus II

Some details:

1. The encoder should include intra mode and inter mode

2. The encoder can encode I frame and P frame.

3. CAVLC is used for entropy encode

4. RDO mode should be implemented and can be chosen based on needs

5. The encoder should have a design to compute the PSNR of YUV components.

6. The code should have notes to help me understand your design.

7. The project should be simulated and synthesized in QuartusII or Xilinx.

8. You should write a document to describe the target and design principle of each module and the relation between different modules.

9. The input of the encoder is a video with QCIF resolution.

10. The output is .264 bits stream. This stream can be decoded correctly with ffmpeg.

11. The last but most important, the encoder should be implemented in Verilog.

Навички: Цифровий дизайн, FPGA, PHP, Архітектура ПЗ, Verilog / VHDL

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Про роботодавця:
( 0 відгуки(-ів) ) Korea, Republic of

ID проекту: #12023739

11 фрілансерів(-и) у середньому готові виконати цю роботу за $950


Hello ! We want to discuss about your project as we have experience in it. What Differentiates us from the other freelancers : # Experience of more than 5 years in Unity 3D, Xcode, CoCoa 2d, Phonegap and major Більше

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Please visit my website to see my experience on this field: [url removed, login to view] Please contact me if we can deal. Thanks

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Dear sir, I have experience with video codecs and FPGA both, I use xilinix and spartan 6 & cyclone -4 boards for development.

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