Create a Generic Code of 8b/10b Encode/Decoder and Generic Scrambler/Descramblers

Job Description :-

1) Go through the PCIe Gen Spec and understand the requirement of 8b/10b Encoder/Decoder and Scrambler/Descrambler

2) Create a Perl-Automated Verilog Code of 8b/10b Encoder/Decoder and Scrambler/Descrambler. In the scrambler, polynomial should be a variable that is passed on from Perl domain to generate Various Verilog Code for Gen3/Gen4/Gen5 Required Scrambler/Descrambler.

3) Similarly create Perl code which can generate 8b/10b Encoder/Decoder and Gen 1-2 scrambler/descrambler.

4) Create individual TBs for these modules that runs multiple interesting patterns through pair ( of scrambler-descrambler OR encoder-decoder) and makes sure that Both pairs are working together fine.

5) Check the results in log/waves, and create regression commandline to make sure they can be rerun in future.

Detailed Requirement :-

1) Preference - Junior 0-4 years of experience engineer or senior around 10 plus years of experience. Experience either in RTL Design or TB/Verification.

2) Experience in VLSI - ASIC/FPGA design with following skillset -

a) Verilog, System Verilog,

b) Perl, Bash, Make

c) working in Unix/Linux Environment and Vim/gvim

3) Following are domain expertise -

a) For junor engineers - Intermediate to efficient capability in skillset above. Added advantage is experience in RTL-design and/or verification experience of small to medium sized blocks.

b) For senior engineers that have design exposure - experience in building microarchitecture, developing RTL code/bug fixes for decent size of module.

c) For senior engineers that have verification exposure - experience in building System Verilog based Testbench development experience, building a testplan.

d) Overall exposure to switch, arbitration, ordering, coherency, PCIe etc is added advantage.

4) Soft skills -

a) For junior engineers - interest in learning the design/verification as one of primary interest of freelancing alonside earning money

b) For junior/senior engineers - passion to explore new domains and happy to solve tough problems.

c) For junior/senior engineers - have good energy to finish work in a timely manner, attention to details and humility to learn from right feedback.

5) Time Availibility -

a) Desirable to have at least 10-15+ hours per week for the work.

b) Able to support next 1-2 months minimum.

Who can Apply :-

1) Fresher/junior engineers looking for an opportunity.

2) People looking for training/upscaling in the domain can apply.

3) People looking to explore in-depth from scratch ASIC design can also apply.

Benefits :-

1) Opportunity to work in complex ASIC product design from scratch.

2) Opportunity to learn alongside experienced and passionate engineers.

3) Monthly Stipend/Remuneration.

4) Facility to work remotely.

Verilog / VHDL Мікроконтролер FPGA Digital ASIC Coding ASIC

ID Проекту: #31018172

Про проект