Verilog program

Закрито Опубліковано %project.relative_time Оплачується при отриманні
Закрито Оплачується при отриманні

I need to make an ALU that can make an output using data_in from an tester .. also the data in can be an header on payload acordoing from 2 other signals

Verilog / VHDL FPGA Мікроконтролер Електроніка Програмування на С

ID Проекту: #22865220

Про проект

9 заявок(-ки) Дистанційний проект Остання активність 4 роки(ів) тому

9 фрілансерів(-и) готові виконати цю роботу у середньому за $25

Lightcanon

I am Digital Electronics engineer and a Teaching Assistant also. I master VHDL/Verilog very well (+4 years exp) and this is my current career. I will give you the task finished efficiently and quickly as well. Example Більше

$45 USD за 1 день
(150 відгуків(и))
7.8
Fpgageek

Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 6 years. Please let me know if the requirement is still there I can work on it. I saw the use project you've attached and yes., I can do Більше

$10 USD за 2 дні(-в)
(33 відгуків(и))
6.1
kptechlead

Hi, glad to bid on your project. I’m an expert on VLSI with VHDL , Verilog , spice , system Verilog. I m a Doctorate in Engineering , I have read your description, i have a 18+ years of experience on development Більше

$40 USD за 2 дні(-в)
(5 відгуків(и))
2.7
chiahoulahbib

Hello, I'am experienced in, Digital / Analog Electronics FPGA altera , Arduino, PIC , AVR , ARM , STM32 , 8051 Programming Single board computers ( Raspbery pi,Orange pi etc) C , C++ , Java , Python , C#, VHDL , VHDL- Більше

$20 USD за 7 дні(-в)
(0 відгуків(и))
0.0
akshayacharya731

Hello , I am a FPGA design engineer with 2 years of experience. I have gone through your code, I can write the logic. I will provide you updated testbench for the whole project. We can negotiate the price. Thank You.

$10 USD за 1 день
(0 відгуків(и))
0.0
SACHINSMUNJI

I am a RTL designer, worked on Projects like Network on Chip, Speech and Image Processing, using Verilog/VHDL. I even work on Chipscope Pro and System Generator on Xilinx ISE and Xilinx Vivado.

$25 USD за 1 день
(1 відгук)
0.0
awais2451985

Hi, I have expertise in Verilog Design and I am also teaching the course. I can do this work for you. I can also guide you about the Verilog Coding.

$30 USD за 3 дні(-в)
(0 відгуків(и))
0.0
Kasunpriyadarsha

I have been working as an electrical and electronic engineer and more familiarized with verilog HDL programming (Vivado Design Suit) as well as c++, Linux, matlab, Labview and etc. So I have a good programming team Більше

$20 USD за 7 дні(-в)
(0 відгуків(и))
0.0
Arvind47G

I can deliver for requirement in 2 days in verilog and vhdl with following good standards of coding means 100% coverage no extra latches

$25 USD за 2 дні(-в)
(0 відгуків(и))
0.0