9-bit CPU: Register file, ALU, and fetch unit

$30-250 USD

Завершено

Опублікований

over 4 years ago

$30-250 USD

Оплачується при отриманні

In this lab assignment, you will design the top level, register file, control decoder, ALU (arithmetic logic unit), data memory, muxes (signal routing switches), lookup tables, and fetch unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want the highest level of your design to be a schematic and [System]Verilog code... if you are intersted in let me know . There is instruction that I will shrae with you.

Verilog / VHDL

Microcontroller

Electronics

Electrical Engineering

FPGA

ID проекту: 21938846

Про проект

7 пропозицій(-ї)

Дистанційний проект

Активність 5 yrs ago

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Доручений:

@raulbehl

Hello! Please check my reviews and profile to know more about me and my work. I’ve helped many students in completing there computer architecture courses and should be able to help you out as well. Please do contact to discuss further! Thank you!

$100 USD за 7 дні(-в)

4,9

(87 відгуки(-ів))

6,3

7 фрілансерів(-и) готові виконати цю роботу у середньому за $136 USD

@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog and system verilog please check my profile also please message me so that we can discuss

$111 USD за 1 день

4,9

(513 відгуки(-ів))

8,2

@uetian09ee506

Hi, i am electrical engineer, i can design the ALU using verilog HDL,....................................

$150 USD за 3 дні(-в)

4,8

(270 відгуки(-ів))

7,3

@ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done with very high difficult project in backend design in FPGA by correct timinig closure for FPGA with 400 Mhz in Virtex Ultrascale+ in some field like mining coin (bitcore, and lyra2rev3) Second, with your requirements, I have finished atlest 10 projects related to CPU with ALU, decoder, Datamemory, instruction memory...All of them run very smooth. Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

$200 USD за 3 дні(-в)

4,9

(94 відгуки(-ів))

6,9

@thasleemkamila

I have well experienced in doing such kind of jobs.......................................................................................................

$50 USD за 3 дні(-в)

4,7

(67 відгуки(-ів))

6,1

@Fpgageek

Hi I have been working on verilog-vhdl and xilinx and altera(intel) FPGAs by more than 6 year. lets discuss the requirements, the price mentioned is negotiable according to your exact requirements. Thanks

$250 USD за 7 дні(-в)