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Hi, I am Avinash Venigalla from India. I hold an Bachelors degree in Electronics and Communication Engineering and also Masters in VLSI Design. I have enclosed a copy of my resume listing my academic training and professional experience. I look forward to hearing from you soon. Project 1: A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. Abstract : In this project we present a high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path), using only three simple repeated CMOS-logicmodule types:an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state look-ahead path pre-pares the counting path's next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. Sincerely, Avinash Venigalla.

Have 9years of Experience in VLSI Design & verification and testing of FPGA & ASIC designs, ASIC to FPGA prototyping, ASIC FEInt synthesis, LEC, linting and virage memory compilers, FPGA (XILINX) Board level designs, synthesis and implementation. Have good experience in verilog coding.