Coding in SystemVerilog and UVM

Dear sir I have more than 9 years experience in RTL design, please check my profile also please message me so that we can discuss best regards

Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. We have a team of 4 members who are well qualified and highly experienced in VLSI codding and simulation. We did many projects for different industrial applications. I understand your requirement and ready to work for you. Please contact me for further discussion.

Hello! I have 2 years of experience in working with UVM and System Verilog code. I've worked with companies like Nvidia and ARM(currently working). Please do contact me to know more about me. Thank you

Hi I have 5 year experience in design verification IP/SOC level and expertise in System verilog and UVM . I can work efficiently for this project.

Hi, I am an ASIC Design Verification Engineer fully employed for one consult company that have been working with mayor market players in ASIC. I have more than 3years knowledge in Verilog ASIC Design, a year in SystemVerilog UVM (in UVM I have been developing some small uVCs). Now I am starting a project in Specman. If you are interested in me, please let me know about the project and we could disscuss. Thank you

What kinda design will you be verifying ? Will you provide the IP ? Do you have an existing verification environment or do you wnat one done from 0 ?

Dear Sir, I would very happy to do your project work. I have a long experience of doing resesrch work in electronics use SystemVerilog/UVM regards

- we are an organization works on ASIC FPGA verification & design. - have more then 4+ years of experience in this domain. - have design verification IP like AXI , I2C , USB protocol. - use of quartus tool to design & verify IP. - provide you daily mail regarding status of work. - system verilog or UVM TB infrastructure which includes : - features - strategies - verification plan.

I worked in multiple international companies.I have long experience in system verilog and good experience in UVM/OVM in sequences and drivers and monitors and make coverage groups for the bins that we want to see its coverage, assertions for the important points in the design. also I will debug the issues and try to give the most efficient solving for it and to try fully randomized cases and specific test scenarios to cover all possible points in this project .

Bachelors in Electronics and communication with 3 years year of working experience in the field of ASIC Verification and aim to enhance my professional skills in a dynamic and stable workplace. Key Skills • Languages : System Verilog, Verilog • Scripting : Linux Shell scripting • Version-control : SVN,Perforce • Protocols : SPI, AHB, JTAG, I2C. • Simulators : ModelSim, Questasim, Cadence Incisive simulator, VCS. • Other tools : Enterprise Planner, Incisive Enterprise Manager (Vmanager), IRSIM, Reveal formal tool. • Technical Skills : UVM, System Verilog Assertion, VIP Development, IP Verification, SOC Verification